CAT24C512 Example with linear address conversion

JonW · Jan 22, 2022, 02:50 PM

24LC512 Procedures and example. Linear memory addressing, Proc Calculates the page and register

'*******************************************************************
'*  Name    : 24LC512.BAS                                         *
'*  Author  : JON WALKER                                           *
'*  Notice  : Copyright (c) 2022 ELECIUM LTD                       *
'*          : All Rights Reserved                                  *
'*  Date    : 22/01/2021                                           *
'*                                                                 *
'*  Version : 0.1                                                  *
'*******************************************************************
device = 18f27k42


Xtal = 64                         ' using pll at full speed (62.5nS/instruction)
Declare All_Digital = TRUE
Declare Optimiser_Level = 0
Declare Hserial_Baud = 115200                ' Set baud rate to 9600
Declare Hserial_RCSTA = %10010000       ' Enable serial port and continuous receive
Declare Hserial_TXSTA = %00100100       ' Enable transmit and asynchronous mode
Declare Hserial_Clear = On                ' Enable Error clearing on received characters      ' Clear the buffer before receiving

SYMBOL MEM_WRITE    = $A0
SYMBOL MEM_READ     = $A1
'-------------------------------------------------------------------------------------
'
'                          PORT Declarations
'
'-------------------------------------------------------------------------------------
    DIM SCL_MEM       AS PORTB.5
    DIM SDA_MEM       AS PORTB.6


'-------------------------------------------------------------------------------------
'
'                          Variable Declarations
'
'-------------------------------------------------------------------------------------

    Dim MEM_DATA       As Byte
    DIM MEM_ADDRESS    AS WORD
    DIM TEMP       AS BYTE
'-------------------------------------------------------------------------------------
'
'                          SET UP PIC
'
'-------------------------------------------------------------------------------------

RRESET:
SETUP:

        ANSELA = 0
        ANSELB = 0
        ANSELC = 0
        CM1CON0 = 0
        LATB = 0
        T3CON =     %00000000
        TRISA =     %00000000   ; ALL OUTPUT
        TRISB =     %00000000   ; ALL OUTPUT
        TRISC =     %10000000   ;
        WPUB =      %00000000   ; NO PULLUPS


RESET_:
        scl_mem = 0
        sda_mem = 0
        GOTO START

'-------------------------------------------------------------------------------------
'
'                          SUBROUTINES  AND PROCEDURES
'
'-------------------------------------------------------------------------------------



'*************************************************************************************
' Name:                       CAT24LC512 MEMORY PROCS
'*************************************************************************************
PROC PACK_ADDR(DAT_IN AS WORD), WORD         ; Converts linear location to Page and Reg
        DIM MEM_REG AS BYTE
        DIM MEM_PAGE AS WORD

        MEM_PAGE = DAT_IN/128         ; PAGE NUMBER
        MEM_REG = (DAT_IN//128)       ; REG IN PAGE
        MEM_PAGE = MEM_PAGE<<7        ; SHIFT PAGE
        RESULT = MEM_PAGE | MEM_REG   ; PACK REGISTER AND RETURN
EndProc

PROC READ_MEM(IN_ADDR AS WORD), BYTE
        DIM RD_ADDR AS WORD

        RD_ADDR = PACK_ADDR(IN_ADDR)
        I2CIN  SDA_MEM,SCL_MEM,MEM_READ,RD_ADDR,[RESULT]
EndProc

PROC WRITE_MEM(IN_ADDR AS WORD, IN_DATA AS BYTE)
        DIM WR_ADDR AS WORD

        WR_ADDR = PACK_ADDR(IN_ADDR)
        I2COut SDA_MEM,SCL_MEM,MEM_WRITE,WR_ADDR,[IN_DATA]
        DELAYMS 5                                             ;DELAY FOR WRITE SEQUENCE
EndProc
'*************************************************************************************




;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;                                              START OF MAIN PROGRAM
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
'>>>START<<<

START:

           MEM_ADDRESS = 20000                       ; PROC WILL WORK OUT PAGE AND REGISTER
           MEM_DATA = 99


           WRITE_MEM(MEM_ADDRESS,MEM_DATA)          ; WRITE DATA TO MEMORY ADDRESS
           MEM_DATA = READ_MEM(MEM_ADDRESS)         ; READ DATA FROM MEMORY ADDRESS

           HRSOUT "ADDRESS ",DEC MEM_ADDRESS," = ",DEC MEM_DATA,13,10

           DELAYMS 200
           GOTO START

END



;***************************  USER SPACE BELOW  *************************
Config_Start
  FEXTOSC = OFF              ;Oscillator not enable
  RSTOSC = HFINTOSC_64MHZ    ;HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:
  CLKOUTEN = OFF             ;CLKOUT function is disable
  PR1WAY = ON                ;PRLOCK bit can be cleared and set only onc
  CSWEN = ON                 ;Writing to NOSC and NDIV is allowe
  FCMEN = ON                 ;Fail-Safe Clock Monitor enable
  MCLRE = INTMCLR            ;If LVP = 0, MCLR pin function is port defined function; If LVP =1, RE3 pin fuction is MCL
  PWRTS = PWRT_OFF           ;PWRT is disable
  MVECEN = ON                ;Multi-vector enabled, Vector table used for interrupt
  IVT1WAY = ON               ;IVTLOCK bit can be cleared and set only onc
  LPBOREN = OFF              ;ULPBOR disable
  BOREN = SBORDIS            ;Brown-out Reset enabled , SBOREN bit is ignore
  BORV = VBOR_2P45           ;Brown-out Reset Voltage (VBOR) set to 2.45
  ZCD = OFF                  ;ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCO
  PPS1WAY = ON               ;PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycl
  STVREN = ON                ;Stack full/underflow will cause Rese
  DEBUG = OFF                ;Background debugger disable
  XINST = OFF                ;Extended Instruction Set and Indexed Addressing Mode disable
  WDTCPS = WDTCPS_31         ;Divider ratio 1:65536; software control of WDTP
  WDTE = OFF                 ;WDT Disabled; SWDTEN is ignore
  WDTCWS = WDTCWS_7          ;window always open (100%); software control; keyed access not require
  WDTCCS = SC                ;Software Contro
  BBSIZE = BBSIZE_512        ;Boot Block size is 512 word
  BBEN = OFF                 ;Boot block disable
  SAFEN = OFF                ;SAF disable
  WRTAPP = OFF               ;Application Block not write protecte
  WRTB = OFF                 ;Configuration registers (300000-30000Bh) not write-protecte
  WRTC = OFF                 ;Boot Block (000000-0007FFh) not write-protecte
  WRTD = OFF                 ;Data EEPROM not write-protecte
  WRTSAF = OFF               ;SAF not Write Protecte
  LVP = ON                   ;Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignore
  CP = OFF                   ;PFM and Data EEPROM code protection disable
Config_End

'**** End of Fuse Configurator Settings ****
'-------------------------------------------------------------------------------

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CAT24C512 Example with linear address conversion

JonW