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I have a variable, precision, low voltage source, 0 to 1V. This passes through two 4.7K series resistors to the +ve input of a unity gain op-amp. In order to generate a pulse I ground the mid point of the two resistors with a low Rdson MOSFET, MOSFET ON = signal off, zero volts.

I am getting coupling between the gate signal (0-5v) and the drain. I turn off my voltage source by turning on the MOSFET. A positive going spike about 5v high appears on the drain as the gate goes high, and it is obviously coming from the gate (the Source is grounded). Once the MOSFET has settled everything is OK.

I have tried a 2N7000 (which has too high Rdson) and the same thing happens. The spike is only a few uS but it is a problem. I could slug it with huge capacitor but I want fast rise/fall times.

Anybody know what's going on?

I would draw the cct but I don't know how and it's pretty simple.

Charlie

Try a P Channel MOSFET. I prefer these most of the time because bringing the Gate to ground turns it on and a pull-up resistor on the Gate keeps the MOSFET switched off by default. I then experiment with the highest value resistor to keep the gate off, so that it draws very little, if any, current, and very little current is required to turn it on, just bring the pin "low".

Also, do you have a series resistor from the microcontroller's pin to the MOSFET's Gate? A direct connection can sometimes cause a MOSFET to fail, and may cause internal spikes because of current surges.

Hi Charlie,
I think it's called Reverse Transfer Capacitance (Crss) or Miller capacitance - basically a small dynamic capacitance between the gate and the drain. Your spike will be proportional to this value and the gate drive voltage.  You could look for a device with very low Crss and ideally low turn on threshold.  NXP did some that were almost like BJTs and were fully on with under 1V drive - just wish I could remember the numbers. Making the 4.7k resistor lower should also reduce the transfer from gate to drain.
Adding a gate drive resistance will slow up the switching time and hence reduce the spike also but may start to impact your switching times if that is important.

Cheers,
David

Charlie - if it is Crss that's causing the spike (as yet unproven) the value will likely be in the order of about 5-10pF.  If you put a capacitor (100pF) from drain to ground it will form a capacitive divider and should greatly reduce the spike you're seeing.  Turn off will be slower but should still only be a few uS and I'm not sure your op-amp is going to be any faster, especially if it's coming out of saturation from the ground rail.

Cheers,
David

Les: I am trying to shunt the mid-point between the two resistors to ground, to "turn off" the reference voltage of 0 to 1V (which then drives a constant current setup). Using a P mosfet I wouldn't have enough volts to turn it on, unless I used a negative rail. Hmm... But I fear I would get the same result. There is no PIC (for once!), the control voltage comes from a pulse generator, 25uS upwards in width.

David: Yes, I am sure that's what it is. I see a similar spike, going negative below ground when the mosfet turns off. I have tried your suggestion but it doesn't make much difference. 1800pF is not bad but it slows the edges too much. I could try different mosfets but I am up against time now as well.

I am trying to alter the potential divider so that I am shunting 10V to ground instead of 1V, but it's not easy.

Thanks for the help, stay tuned.....

Charlie

which opamp an FET do you use?
opamp single +5V supply?

Charlie - 1800pF sounds massive unless you're running a large power FET which will have a much larger Crss.  You shouldn't need anything like that amount.   
With a 1V reference and 4.7k series resistance a 2N7000 FET should be fine. With a RdsOn of say 5ohms you're looking at just over 1mV when the FET is on - I would think that's less than your input offset voltage of the op-amp.
Something doesn't quite add up here or maybe I've misunderstood your circuit.   I'm assuming it's something like the attached.

Cheers,
David

Charlie - is your main current sinking power FET connected when observing this effect?  I don't know what sort of current you are sinking but when the power FET turns off there will be the classic I^2.L kick back  - similar to turning off a relay without a reverse pole diode across it.   If the current is modestly high (like several amps) then it doesn't take much wiring inductance to cause a spike on the supply but I don't know if this can find its way in to your reference circuit.

Cheers,
David

Your circuit is spot on David, except the 1V is variable down to zero. The op-amp being driven is part of a constant current cct and does not saturate, it's ready for a nice sharp rise time signal. There is virtually no current involved. I tried a small power mosfet because I only have 2N7000 in the smaller size range.

The results with the 2N7000 show the nasty spikes. I reckon the reason is as follows: if the voltage on the drain is say 0.5V and the drive is 5V, then there will always be that spike, it will be the same size as the gate drive. In fact, if I set the voltage into the first resistor to zero, there are still positive and negative 5V spikes appearing on the drain of the 2N7000. 100pF doesn't make much difference.

I'm trying to arrange a bigger swing at the centre point of the resistors, and then divide the result by 10.

Hi Charlie,
I am surprised it's proving difficult to reduce but then I guess the Miller capacitance gets multiplied by the gm.Rl of the circuit.  Reducing the 4.7k resistor from the reference voltage (say 1k) should directly change the spike amplitude you're seeing.  Similarly reducing the gate drive should also directly change the amplitude of the spike but you would need to know how low you can still switch correctly.  Some FETs are fully characterized for 1.2V switching.
I had a very similar requirement quite recently but I had a PIC doing the pulse generation (10mS) at regulated 5V level then divided that down to 1V for the op-amp.   I was wanting a 10A pulse.
Going higher in the reference voltage will mask the effect but you still need to keep the first resistor reasonably low in value to reduce the multiplication of the Miller capacitance.
I can only wish you good luck.

Cheers,
David

Thanks David, I agree that's it's a bit of a bugger. I think I have solved it. The 0-1V comes from a potential divider which is on the output of a 10 turn pot which is fed from a 2.5V voltage ref chip. The ref chip is fed from 18V with a 2.2K resistor (just like a zener diode setup). So I am going to split that 2.2K into 2x1K resistors, and use the mosfet to ground the point between the two 1K's. 18mA will flow in the top 1K but the output from the ref setup will now be zero. I will no longer try shunting the mid point of the 2 4.7K's. Any spikes from the mosfet shouldn't appear in the output of the ref chip but I don't expect to see any at these voltage levels.

I have checked the datasheet of the FAN431A 2.5V ref chip and it comes to life within <1uS, which is fine. This causes another problem but I can sort that with a some quiet time and a glass or two of Pinot Grigio.

Thanks for your help, we can put it down to experience that spikes from the gate drive of a mosfet will appear on the drain under certain conditions. This actually explains a strange thing that I came across a few years ago and never resolved.

Best
Charlie

Hello Charlie,
Sounds like a plan you have there.  Any reason you can't put the FET directly across the reference device and reduce the current to 9mA and save adding another resistor?
Hope the rest of the project goes smoothly for you.
Electronics - the art of compromise.......

Cheers,
David

Yes, I thought about doing that, but the reference is only 2.5V so I may well have had the same trouble. No worries about the amount of power I use, within reason, it's not battery powered.

"The art of compromise", I like that. I've been in the electronics game since valves were popular and I still get caught out. This project is driving constant power pulses into various resistances, all below about 20 ohms and 10 watts. I can't say much more than that.

Getting old isn't helping either, I used to have a good memory but it's not so good now. This work keeps the little grey cells busy which I think is important. I am also a volunteer at The National Museum of Computing at Bletchley Park. We have a great team of good guys and it's good fun and very stimulating.

Are you designing in the commercial electronics field?

Charlie

Hello Charlie,

I think David is right and the effect is due to the Gate-to-Drain capacitance existing in all MOSFETs which is causing the coupling.

In your case you have a fast rising dV/dT and because of the other parasitic capacitance between the gate and the source some voltage appear on the drain through the Gate-to-Drain capacitance.

Just a question, since you are shunting the voltage between the two resistor can't you use a small switching BJT?

I did a simulation of your circuit with LTspice.  It looks like the source of your >1v spike is coming from the OP-AMP - assuming its powered by 5v like the gate of the MOSFET connected to the series 4.7k resistors. Placing a 0.1u at the junction of the mosfet and the two 4.7k resistor eliminates the spike but limits the 1v rise back from 0 to > 1ms. Adding 100p cap at the +ve combined with 1n cap at the junction shortens turn on time to 88uS and appears to eliminate the + spike but adds a -0.5v spike at MOSFET = OFF.  Don't know which is worse but I think you may find your solution adding caps to your in OP-AMP.  Added LTspice .asc you can play with.

Quote from: charliecoutas on Aug 29, 2021, 02:54 PMYes, I thought about doing that, but the reference is only 2.5V so I may well have had the same trouble. No worries about the amount of power I use, within reason, it's not battery powered.

"The art of compromise", I like that. I've been in the electronics game since valves were popular and I still get caught out. This project is driving constant power pulses into various resistances, all below about 20 ohms and 10 watts. I can't say much more than that.

Getting old isn't helping either, I used to have a good memory but it's not so good now. This work keeps the little grey cells busy which I think is important. I am also a volunteer at The National Museum of Computing at Bletchley Park. We have a great team of good guys and it's good fun and very stimulating.

Are you designing in the commercial electronics field?

Charlie

Hello Charlie,
Putting the FET across the reference should work ok.  The reference is the ideal shunt regulator so should clamp the spike.  It should also greatly lower the gain of the FET (gm.Rl) rather than having a resistive load.

It's great work you're doing at Bletchley Park.  I believe Alan Touring's image is going on a coin - finally some national recognition for a great man.
I'm a very retired electronics engineer who also cut his teeth on valves.
Good luck with the project and I wish you well preserving the code breaking heritage you're involved with.

Best regards,
David

trastikata: I need to clamp the voltage right down to zero (well a millivolt of two). A BJT would have some Vce surely?

xldaedulus: No, the op-amp is not powered by the same supply. I'm sure it's the gate to drain cap that's doing it, could you try LTspice driving the gate of a mosfet with just a resistor from drain to source and see what happens? Yes, a few 1000pF will solve the problem but I need rise times of <5uS. Thanks for trying LTspice, I've never walked that path.

David: Yes, I have tried shunting the much higher voltage to the reference and that looks good. Even if there is a spike it is overruled by the higher voltages "outside" the reference source. Turing is on one of the banknotes and a coin will be a good thing too. It's a lot of fun and head-scratching at the museum. When you think that in 1943 Tommy Flowers built a machine with 1500 valves (Colossus) and got it working in a short time with 'scopes that were very basic, it does make you sit back and think. When it goes wrong we often have to think quite hard even with our fancy scopes and logic analysers.

Thanks guys, this is a GREAT forum.

Charlie

Charlie - have you tried the FET directly across the FAN431A?  It should be very good as the reference has a very low dynamic impedance.
At low currents the VceSat of a BJT will get quite low (50mV?) but would work fine if used across the reference or for clamping the feed to the reference. 

I might wait for a coin with Touring's image on it  - it would look good next to my crown with Churchill on it.
1500 valves?  That's a lot of filament power.  I won't ask what the "up" time is on that lot.....
I admire you for preserving this important part of history.

Best regards,
David

Quotethis is a GREAT forum.

I could not agree more Charlie. It is a wonderful forum filled with wonderful people who take the time to help where they can. That is what life should be like in the "real" world as well.

David... I'm having big problems using an FET as an auto volume control. I have it working on the input of the amplifier, but when it gets to low volume it distorts. I've tried all sorts of feedback and capacitors on its pins and different FET types etc, but I just cannot get it to work as it should on low volumes. I know this can be a problem with FETs, but I'm sure there is a workaround somewhere. I do not have an op-amp (for cost purposes) so I cannot use the FET as the gain, so it is operating with the volume control pot on the amplifier's input. Any ideas please? It is for my story painter project, so as the stories are playing, the volume drops slightly over time, so the child falls asleep as the volume of thier favourite stories decreases, but I have to keep the audio quality intact.

Hello Les,
Both JFETs and BJTs can be used for audio level control but the trick is to keep the audio level as low as possible - ideally less than 20mV.  This sort of level lends itself to microphone amplifiers where the active control device is only seeing a small level and is normally followed by a gain stage to get up to line level but this isn't a good option for you.
If you refer to the attached circuit there is an AVC circuit which is quite well done.  Firstly it's only having to control very low mic signals and secondly it has drain to gate feedback applied around the JFET in  2:1 ratio (2x 100k resistors) which greatly reduces the square law characteristic and eliminates distortion.  We used this same topology for very low distortion Wein bridge oscillators, effectively replacing the classic thermistor control of earlier times. Note that the circuit shown appears to have the filter capacitor for the output rectification reversed.  With no output signal from the op-amp the JFET has no bias and its gate is near ground and therefore it's hard on and trying to increase the gain.  As the level increases the diodes will produce an increasing -ve level on the gate and start turning the JFET off.  The 22uFd capacitor should be connected the other way around.
A similar approach can be done with BJTs and they don't require the feedback but the level across them needs to be even lower than the JFET circuit.   Rather than using them in the feedback circuit of an op-amp gain stage they can be used at the input of a gain stage along with a suitable series resistor. As the base goes +ve the device clamps the signal and reduces the gain.
Lastly I've added a rather basic diode amplitude modulator.  It also needs low (ish) levels and the circuit as shown produces a very pleasant decaying chime sound.
Over the decades I've all three methods.  BJTs for cassette tape automatic microphone level controls, JFETs for the audio oscillators and the diodes for a public address announcement system that emulated 4 xylophone gongs.
Surely there has to be a more digital approach these days that's not too complex.

Cheers,
David