Positron BASIC Community

Hello all,

I was getting inconsistent results reading back from display memory and after I ruled out code problems, I started suspecting SPI problem. After hooking the USB oscilloscope, the problem got apparent - voltage levels.

However I am wondering what could cause the strange voltage output from the display?

Is the red trace the SPI data from the display? I assume the yellow trace is a clock from you?

Charlie

Quote from: charliecoutas on May 29, 2026, 12:18 PMIs the red trace the SPI data from the display? I assume the yellow trace is a clock from you?

That's correct Charlie, yellow is clock line and red is the SPI output from displays.

That is an odd one. I know it is not usually required but does pull up resistor improves things?

Hi,
Stephen beat me to it, I was thinking a pull down as the data when idle is neither 0 or 1?

Bob

First thing I've tried, 10k Pull-Up and Down but there's virtually no difference. Something inside the level shifting or the TFT driver IC is causing it.

That looks like there are two outputs driving the line to me.
Are those with the SPI out of the display connected to the pic?
Are you sure the pic SPI in is actually in input mode?

Hello tumbleweed,

this is the SPI output connected to the PIC SPI input. It both appears in hardware and software (bit banging) mode - that part is correct.

Meanwhile I asked ChatGPT - how much I can trust the answer is questionable, but that's what I got as an explanation:

==================================
Because the ST7789 output stage is almost certainly not continuously driving the line during the read cycle.

What you are seeing is not "random voltage generation", but the analog result of:

output enable toggling,
weak output drive,
internal bus multiplexing,
and line capacitance.

The important realization is:

A CMOS output pin is not always in one of two ideal states.

Internally it transitions between:

PMOS on,
NMOS on,
both off,
both partially conducting,
bus handover states.

And the ST7789 read path is especially ugly because the controller is fundamentally optimized for writes.

The waveform strongly suggests this exact mechanism:

During reads the ST7789 intermittently tri-states the output

Meaning:

for part of the bit time:
output transistor actively drives,
then:
output disconnects internally,
then:
re-engages for next phase.

When disconnected:

the line voltage is determined by:
parasitic capacitance,
leakage,
probe loading,
internal resistance.

That produces the "half-voltage plateaus".

Why this happens specifically in ST7789

The ST7789 internally does not have a native SPI memory architecture.

Internally it has:

GRAM,
parallel buses,
timing generators,
scan logic.

SPI readback is effectively a serialized export path layered on top.

So during a read:

Internal GRAM data fetched
Loaded into serializer
Output stage enabled
Output stage disabled
Next internal transfer occurs

This can create tiny Hi-Z windows between bits or groups of bits.

Normally:

hardware SPI ignores this,
because it samples later in the bit cell.

Your oscilloscope, however, reveals the analog transitions.
==================================

I don't know if this helps, but there are 4 distinct voltage levels.

I am playing with epoxy resin as a garden tabletop finish. ChatGPT has given me some very good advice.
It (he/she?) even said it was "Looking forward to seeing the final result".

Charlie

I agree it looks like bus contention.  Is there only one display/device on the MISO line?

Quote from: streborc on May 29, 2026, 06:33 PMI agree it looks like bus contention.  Is there only one display/device on the MISO line?

Yes, there's only one - host and 1 slave device.

The AI blurb seems to be focusing on very short term effects-

the line voltage is determined by:
parasitic capacitance,
leakage,
probe loading,
internal resistance.

There's no obvious leading /trailing edge rounding that would indicate tristate logic with high bus or probe capacitance and the various data levels are instantly set.
The very first capture shows the data line idling high at 2.2V with odd data reaching the expected 3.3V and other data highs only reaching 0.8V.   The second capture shows the data line idling at 0.8V with some data at 0.8V and some at 3.3V.  The idling period is not a short term transient effect and would seem to be driven to these odd voltages with relatively low impedance - like two outputs of somewhat different source impedance driving a common point.
So where does 2.2V come from?  Does the SPI data pin on the display have any other functions that may need to be turned off?
I'm sure there will be great interest in the next instalment of this mystery.

Cheers,
David

Mystery solved. 

You guys were right, today on a fresh mind I looked again and I realized there's a touch IC on those panels internally connected to the same SPI bus.

I completely forgot to set the touch CS line to output and make it high level, effectively left floating, thus as you correctly stated, it is indeed 2 devices sharing the same line.

Thank you all for showing me the right direction. 

The perils of midnight engineering......
Great to hear it's all sorted but I'm sure you would have tracked it down yourself without us assistant guessers.

To repeat what David said, but in a slightly different way: it couldn't have happened to a better chap!

Charlie