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Setting PLL for 18F14k22

Started by Fanie, Today at 05:59 PM

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Fanie

I only get 16MHz, but would like the PLL to run it at 64MHz.  Tested with the LED method, four times slower.

It's probably going to be one of the stupid settings I miss.

Device = 18F14K22           '18F14K50    ' 24FJ16MC102     '32CM5164JH00032T

Xtal = 64

Config_Start
   FOSC = IRC ; Internal RC oscillator
   'FOSC = HS      ; HS oscillator                     Neither of these makes a difference...
   PLLEN = On       ; Oscillator multiplied by 4
   PCLKEN = On     ; Primary clock is under software control     
   FCMEN = OFF      ; Fail-Safe Clock Monitor disabled         
   IESO = On        ; Oscillator Switchover mode enabled
   PWRTEN = On      ; PWRT enabled
   BOREN = Off      ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
   BORV = 30        ; VBOR set to 2.2 V nominal
   WDTEN = OFF      ; WDT is controlled by SWDTEN bit of the WDTCON register
   WDTPS = 64
   MCLRE = OFF      ; RA3 input pin enabled; MCLR disabled
   HFOFST = On      ; The system clock is held off until the HF-INTOSC is stable.
   STVREN = On      ; Stack full/underflow will cause Reset
   LVP = Off ; (Single-Supply icsp ?) Low Voltage programming disabled
   BBSIZ = OFF ; 1kW boot block size
   XINST = Off ; Instruction set extension and Indexed Addressing mode enabled
   Cp0 = On     ; Block 0 code-protected
   CP1 = On         ; Block 1 (002000-003FFFh) code-protected
   CPB = On         ; Boot block (000000-0007FFh) code-protected
   CPD = On         ; Data EEPROM code-protected
   WRT0 = OFF       ; Block 0 (000800-001FFFh) not write-protected
   WRT1 = OFF       ; Block 1 (002000-003FFFh) not write-protected
   WRTB = OFF       ; Boot block (000000-0007FFh) not write-protected
   WRTC = OFF       ; Configuration registers (300000-3000FFh) not write-protected
   WRTD = OFF       ; Data EEPROM not write-protected
   EBTR0 = OFF      ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
   EBTR1 = OFF      ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
   EBTRB = OFF      ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Config_End

trastikata

Try this:

Device = 18F14K22
Declare Xtal = 64

Main:
    OSCCON = 0x72       'Set Internal Oscillator Frequency to 16 MHz and select Internal oscillator block
    OSCTUNE.6 = 1       'PLL enabled (for HFINTOSC 8 MHz and 16 MHz only)
End

Config_Start
   FOSC = IRC ; Internal RC oscillator
   PLLEN = On       ; Oscillator multiplied by 4
   PCLKEN = On     ; Primary clock is under software control     
   FCMEN = OFF      ; Fail-Safe Clock Monitor disabled         
   IESO = On        ; Oscillator Switchover mode enabled
   PWRTEN = On      ; PWRT enabled
   BOREN = Off      ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
   BORV = 30        ; VBOR set to 2.2 V nominal
   WDTEN = OFF      ; WDT is controlled by SWDTEN bit of the WDTCON register
   WDTPS = 64
   MCLRE = OFF      ; RA3 input pin enabled; MCLR disabled
   HFOFST = On      ; The system clock is held off until the HF-INTOSC is stable.
   STVREN = On      ; Stack full/underflow will cause Reset
   LVP = Off ; (Single-Supply icsp ?) Low Voltage programming disabled
   BBSIZ = OFF ; 1kW boot block size
   XINST = Off ; Instruction set extension and Indexed Addressing mode enabled
   Cp0 = On     ; Block 0 code-protected
   CP1 = On         ; Block 1 (002000-003FFFh) code-protected
   CPB = On         ; Boot block (000000-0007FFh) code-protected
   CPD = On         ; Data EEPROM code-protected
   WRT0 = OFF       ; Block 0 (000800-001FFFh) not write-protected
   WRT1 = OFF       ; Block 1 (002000-003FFFh) not write-protected
   WRTB = OFF       ; Boot block (000000-0007FFh) not write-protected
   WRTC = OFF       ; Configuration registers (300000-3000FFh) not write-protected
   WRTD = OFF       ; Data EEPROM not write-protected
   EBTR0 = OFF      ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
   EBTR1 = OFF      ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
   EBTRB = OFF      ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
Config_End

Pepe

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