Timer1 Gated Mode and TMR1IE?

[trastikata]

Hello all,

Do you know if the Interrupt Enable on Timer1 will halt the timer count when in Gated Mode and the timer overflows.

Otherwise said can I use the Overflow Interrupt Flag to count the number of overflows between two gate events without loosing clock cycles in the total count?

[Stephen Moss]

As you have not specified the device I cannot be certian of its operation but to my knowledge the timer interrupt never stops/interrutps the timer count. As long as the timer is on it should continue to count for every clock pulse recieved, all the timer interrupt should do it set the interrupt flag and trigger the jump the code to the interrupt vector.

As for the second part it depends on what is being gated and how, if it is the clock source to Timer1 that is being gated, then Timer1 will only receive clock singals while the gate is in the active state (allowing clock signals to pass to Timer1).
Therefore, if the timer count is either cleared or read at the start of the active period you should be able to count the number of overflow events that occure during the acive gate period provided you have a way of detecting the active gate period, such as an ICO to indicate when to read the overflow count. Otherwise you will not know if the current Timer1 interrupt refers to active gate period 1, 2, 3, and so on, only the combined total of all active gate periods upto the current point.

[trastikata]

Thank you Stephen Moss.

The device in question is PIC18F26J50. What I am designing is precise frequency counter using the GPS 1PPM output for calibration of the absolute offset in a TCXO.

- The frequency output from the TCXO is fed to the T1CKI pin and used as a clock source for Timer1.
- Timer1 is set as counter with gate control in synchronous mode
- The gate control is set to Single pulse Toggle mode
- Signal from the GPS 1PPM output is fed to T1G pin for gate control

So the device will count the number of TCXO clocks at the T1CKI pin between two rising edges of the GPS 1PPM signal fed to the T1G pin..

However the Timer1 has only 16b counter so I'll have to count the Timer1 overflow interrupts (increment a variable in ISR) between two 1PPM rising edges to get the total number of TCXO clocks. 

Thus my question was - when in this mode, the Timer1 overflows, does it get stalled for any reason where clocks to Timer1 might be lost? I know the counter circuit normally shouldn't be interfered, but still looking through the logic diagrams I am not sure.

Thanks