Hex file editor

[DaveS]

Been without a car for a week, so I knocked this up. Asm decoding to add, any suggestions.
At the moment you can change fuse settings ,change the epprom data and save to hex file, also store the eeprom data to a file.
Might look at using the Positron fuse settings so you could export to Positron.

[trastikata]

Asm decoding to add, any suggestions.

Would be very useful if you can add cycles for each instruction row.

[DaveS]

Asm decoding to add, any suggestions.

Would be very useful if you can add cycles for each instruction row.

I will have a look at that.
I have done 18F asm disassembly, I will test using that.
I'm using AI, feels like cheating. but the results are fast and catches a lot of things I may of overlooked.

DaveS

[DaveS]

I have added Cycle count to asm output as line comment.
Any more suggestions are welcome.

DaveS

[trastikata]

Instruction cycles are great addition!

[DaveS]

I need help to continue. 
A code template to use the ouput in Positron bas file and a code template to use the output to send direct to an assembler.
I think I over complicated the fuse output.
I know I have to add the SFRs for assembler.
The Code is from the compiled Thermistat_High-Low.bas hex file in the samples folder

DaveS

Code Select Expand



  nop ; cycles: 1, count: 1
  nop ; cycles: 1, count: 2
  goto    L_0000B4 ; cycles: 2, count: 4
L_000008:
  bcf     0, 3 ; cycles: 1, count: 5
  movf    3, W ; cycles: 1, count: 6
  btfsc   STATUS, 2 ; skips next 1-word instruction, cycles: 1/2/3, count: 7
  bsf     0, 3 ; cycles: 1, count: 8
  movlw   5 ; cycles: 1, count: 9
  movwf   2 ; cycles: 1, count: 10
  movlw   39 ; cycles: 1, count: 11
  movwf   7 ; cycles: 1, count: 12
  movlw   16 ; cycles: 1, count: 13
  rcall   L_000034 ; cycles: 2, count: 15
  movlw   3 ; cycles: 1, count: 16
  movwf   7 ; cycles: 1, count: 17
  movlw   232 ; cycles: 1, count: 18
  rcall   L_000034 ; cycles: 2, count: 20
  clrf    7 ; cycles: 1, count: 21
  movlw   100 ; cycles: 1, count: 22
  rcall   L_000034 ; cycles: 2, count: 24
  clrf    7 ; cycles: 1, count: 25
  movlw   10 ; cycles: 1, count: 26
  rcall   L_000034 ; cycles: 2, count: 28
  movf    8, W ; cycles: 1, count: 29
  bra     L_000042 ; cycles: 2, count: 31
L_000034:
  movwf   6 ; cycles: 1, count: 32
  movf    9, W ; cycles: 1, count: 33
  movwf   5 ; cycles: 1, count: 34
  movf    8, W ; cycles: 1, count: 35
  movwf   4 ; cycles: 1, count: 36
  rcall   L_00007C ; cycles: 2, count: 38
  movf    4, W ; cycles: 1, count: 39
L_000042:
  movwf   4 ; cycles: 1, count: 40
  dcfsnz  2, F ; skips next 1-word instruction, cycles: 1/2/3, count: 41
  bcf     0, 3 ; cycles: 1, count: 42
  movf    3, W ; cycles: 1, count: 43
  bz      L_000050 ; cycles: 1/2, count: 44
  subwf   2, W ; cycles: 1, count: 45
  bc      L_00005E ; cycles: 1/2, count: 46
L_000050:
  movf    4, W ; cycles: 1, count: 47
  btfss   STATUS, 2 ; skips next 1-word instruction, cycles: 1/2/3, count: 48
  bcf     0, 3 ; cycles: 1, count: 49
  btfsc   0, 3 ; skips next 1-word instruction, cycles: 1/2/3, count: 50
  bra     L_00005E ; cycles: 2, count: 52
  addlw   48 ; cycles: 1, count: 53
  bra     L_000078 ; cycles: 2, count: 55
L_00005E:
  return ; cycles: 2, count: 57
L_000060:
  clrf    EECON1 ; cycles: 1, count: 58
  bsf     EECON1, 7 ; cycles: 1, count: 59
L_000064:
  tblrd*+ ; cycles: 2, count: 61
  movf    TABLAT, W ; cycles: 1, count: 62
  bz      L_00006E ; cycles: 1/2, count: 63
  rcall   L_000070 ; cycles: 2, count: 65
  bra     L_000064 ; cycles: 2, count: 67
L_00006E:
  return ; cycles: 2, count: 69
L_000070:
  btfss   PIR1, 4 ; skips next 1-word instruction, cycles: 1/2/3, count: 70
  bra     L_000070 ; cycles: 2, count: 72
  movwf   TXREG ; cycles: 1, count: 73
  return ; cycles: 2, count: 75
L_000078:
  btfsc   1, 2 ; skips next 1-word instruction, continues at L_00007C, cycles: 1/2/3, count: 76
  bra     L_000070 ; cycles: 2, count: 78
L_00007C:
  clrf    9 ; cycles: 1, count: 79
  clrf    8 ; cycles: 1, count: 80
  movlw   16 ; cycles: 1, count: 81
  movwf   PRODL ; cycles: 1, count: 82
L_000084:
  rlcf    5, W ; cycles: 1, count: 83
  rlcf    8, F ; cycles: 1, count: 84
  rlcf    9, F ; cycles: 1, count: 85
  movf    6, W ; cycles: 1, count: 86
  subwf   8, W ; cycles: 1, count: 87
  movf    7, W ; cycles: 1, count: 88
  subwfb  9, W ; cycles: 1, count: 89
  bnc     L_00009E ; cycles: 1/2, count: 90
  movf    6, W ; cycles: 1, count: 91
  subwf   8, F ; cycles: 1, count: 92
  movf    7, W ; cycles: 1, count: 93
  subwfb  9, F ; cycles: 1, count: 94
  bsf     STATUS, 0 ; cycles: 1, count: 95
L_00009E:
  rlcf    4, F ; cycles: 1, count: 96
  rlcf    5, F ; cycles: 1, count: 97
  decfsz  PRODL, F ; skips next 1-word instruction, cycles: 1/2/3, count: 98
  bra     L_000084 ; cycles: 2, count: 100
  movf    4, W ; cycles: 1, count: 101
  return ; cycles: 2, count: 103
  setf    84 ; cycles: 1, count: 104
  dw      29285 ; unrecognized or unsupported
  addwfc  109, W ; cycles: 1, count: 105
  addwfc  61, W ; cycles: 1, count: 106
  nop ; cycles: 1, count: 107
L_0000B4:
  clrf    0 ; cycles: 1, count: 108
  bsf     BAUDCON, 3 ; cycles: 1, count: 109
  movlw   160 ; cycles: 1, count: 110
  movwf   SPBRG ; cycles: 1, count: 111
  movlw   1 ; cycles: 1, count: 112
  movwf   SPBRGH ; cycles: 1, count: 113
  movlw   32 ; cycles: 1, count: 114
  movwf   TXSTA ; cycles: 1, count: 115
  movlw   144 ; cycles: 1, count: 116
  movwf   RCSTA ; cycles: 1, count: 117
  movlb   0 ; cycles: 1, count: 118
  clrf    ANSEL ; cycles: 1, count: 119
  clrf    ANSELH ; cycles: 1, count: 120
  clrf    CM1CON0 ; cycles: 1, count: 121
  clrf    CM2CON0 ; cycles: 1, count: 122
  clrf    SLRCON ; cycles: 1, count: 123
  movlw   60 ; cycles: 1, count: 124
  movwf   ADCON0 ; cycles: 1, count: 125
  clrf    ADCON1 ; cycles: 1, count: 126
  movlw   130 ; cycles: 1, count: 127
  movwf   ADCON2 ; cycles: 1, count: 128
  movlw   1 ; cycles: 1, count: 129
  movwf   ANSEL ; cycles: 1, count: 130
  clrf    ANSELH ; cycles: 1, count: 131
  bsf     ADCON0, 0 ; cycles: 1, count: 132
  bsf     ADCON0, 1 ; cycles: 1, count: 133
L_0000E8:
  btfsc   ADCON0, 1 ; skips next 1-word instruction, continues at L_0000EC, cycles: 1/2/3, count: 134
  bra     L_0000E8 ; cycles: 2, count: 136
L_0000EC:
  movlw   195 ; cycles: 1, count: 137
  andwf   ADCON0, W ; cycles: 1, count: 138
  iorlw   0 ; cycles: 1, count: 139
  movwf   ADCON0 ; cycles: 1, count: 140
  bsf     ADCON0, 1 ; cycles: 1, count: 141
L_0000F6:
  btfsc   ADCON0, 1 ; skips next 1-word instruction, cycles: 1/2/3, count: 142
  bra     L_0000F6 ; cycles: 2, count: 144
  movff   ADRESL, 13 ; cycles: 2, count: 146
  movff   ADRESH, 14 ; cycles: 2, count: 148
  movlw   0 ; cycles: 1, count: 149
  movwf   TBLPTRH ; cycles: 1, count: 150
  movlw   170 ; cycles: 1, count: 151
  movwf   TBLPTRL ; cycles: 1, count: 152
  rcall   L_000060 ; cycles: 2, count: 154
  movlw   4 ; cycles: 1, count: 155
  movwf   1 ; cycles: 1, count: 156
  clrf    3 ; cycles: 1, count: 157
  movff   14, 9 ; cycles: 2, count: 159
  movff   13, 8 ; cycles: 2, count: 161
  rcall   L_000008 ; cycles: 2, count: 163
  movlw   13 ; cycles: 1, count: 164
  rcall   L_000070 ; cycles: 2, count: 166
  movlw   88 ; cycles: 1, count: 167
  subwf   13, W ; cycles: 1, count: 168
  movlw   2 ; cycles: 1, count: 169
  subwfb  14, W ; cycles: 1, count: 170
  bc      L_000134 ; cycles: 1/2, count: 171
  bcf     TRISB, 1 ; cycles: 1, count: 172
  bsf     LATB, 1 ; cycles: 1, count: 173
  bcf     TRISB, 0 ; cycles: 1, count: 174
  bcf     LATB, 0 ; cycles: 1, count: 175
  bra     L_000150 ; cycles: 2, count: 177
L_000134:
  movlw   239 ; cycles: 1, count: 178
  subwf   13, W ; cycles: 1, count: 179
  movlw   2 ; cycles: 1, count: 180
  subwfb  14, W ; cycles: 1, count: 181
  bnc     L_000148 ; cycles: 1/2, count: 182
  bcf     TRISB, 1 ; cycles: 1, count: 183
  bcf     LATB, 1 ; cycles: 1, count: 184
  bcf     TRISB, 0 ; cycles: 1, count: 185
  bsf     LATB, 0 ; cycles: 1, count: 186
  bra     L_000150 ; cycles: 2, count: 188
L_000148:
  bcf     TRISB, 0 ; cycles: 1, count: 189
  bcf     LATB, 0 ; cycles: 1, count: 190
  bcf     TRISB, 1 ; cycles: 1, count: 191
  bcf     LATB, 1 ; cycles: 1, count: 192
L_000150:
  bra     L_0000EC ; cycles: 2, count: 194
L_000152:
  bra     L_000152 ; cycles: 2, count: 196
;---------------------------------------------
__eof
;---------------------------------------------
; EEPROM DATA
;---------------------------------------------
; CONFIG FUSES
__config config1h, FOSC_HSPLL_HS_1 & FCMEN_OFF_1 & IESO_OFF_1
__config config2l, PWRT_OFF_2 & BOR_OFF_2 & BORV_0_2 & VREGEN_OFF_2
__config config2h, WDT_OFF_2 & WDTPS_128_2
__config config3h, CCP2MX_ON_3 & PBADEN_OFF_3 & LPT1OSC_OFF_3 & MCLRE_ON_3
__config config4l, STVREN_OFF_4 & LVP_OFF_4 & XINST_OFF_4 & DEBUG_OFF_4
__config config5l, CP0_OFF_5 & CP1_OFF_5 & CP2_OFF_5 & CP3_OFF_5
__config config5h, CPB_OFF_5 & CPD_OFF_5
__config config6l, WRT0_OFF_6 & WRT1_OFF_6 & WRT2_OFF_6 & WRT3_OFF_6
__config config6h, WRTC_OFF_6 & WRTB_OFF_6 & WRTD_OFF_6
__config config7l, EBTR0_OFF_7 & EBTR1_OFF_7 & EBTR2_OFF_7 & EBTR3_OFF_7
__config config7h, EBTRB_OFF_7
    end