Very high absolute accuracy frequency counter using GPS

[trastikata]

Hello,

here's an example where I am using the GPS module's 1PPS output pin as reference source for high absolute accuracy frequency counter.

Explanation:

Most GPS modules have an output pin, called 1PPS which will output 1 Pulse Per Second once they have found enough satellites for a valid GPS fix. This output is synchronized with the satellite's atomic clocks and has device accuracy about few nano-seconds. Often this pin is used for LED blinking to indicate the GPS has found the satellite signal.

- We can port this 1PPS signal to the MCU Timer1 Gate (T1G) pin and connect the frequency source of interest as clock source for Timer1 using the T1CKI pin.

- Then we use Timer1 in GATE SINGLE PULSE AND TOGGLE COMBINED MODE - basically the signal rising edge on T1G pin will trigger entirely hardware controlled start and stop condition for the Timer1 counter without loosing any cycles for software interrupt routines. 



- Because 1PPS takes 1 second, we need to add a Timer1 overflow counter to get the exact pulse count, received at the T1CKI pin.

- Of course we need to wait for the GPS module to get a valid satellite fix and start pulsing the 1PPS pin.

In the following code example, I am porting the T1G (Timer1 Gate input) to PPS pin #12 and using it to measure the clock from a TCXO in a RF transmitter for initial absolute accuracy.

Code Select Expand

Device = 18F25J50

Declare Xtal = 48

Dim wTimer1 As TMR1L.Word 
Dim wTMR1Overflow As Word
Dim dPulseCount As Dword

Symbol TMR1ON = T1CON.0
Symbol TMR1IF = PIR1.0
Symbol T1GGO = T1GCON.3

On_Interrupt GoTo Isr
GoTo Main

Isr:
    Context Save
        If TMR1IF = 1 Then      'Timer1 Overflow flag
            Inc wTMR1Overflow   'Increment overflow counter
            TMR1IF = 0          'Clear the Timer1 Overflow flag
        EndIf
    Context Restore
   
Main:
    'Set Peripheral Pin Select T1G to RP12
    SetPPS()

    'Set Timer1 registers for GATE SINGLE PULSE AND TOGGLE COMBINED MODE
    SetCounter()
   
   
    'Wait for rising edges at the 1PPS pin
    While T1GGO = 1 : Wend
   
    'Total pulse count for 1 second
    dPulseCount = (wTMR1Overflow*65536) + wTimer1
   
    End
   
   
Proc SetCounter()
    '1 = Timer1 counting is controlled by the Timer1 gate function
    '1 = Timer1 gate is active-high (Timer1 counts when gate is high)
    '1 = Timer1 Gate Toggle mode is enabled
    '1 = Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate
    '0 = Timer1 gate single pulse acquisition has completed or has not been started
    '0 = T1GVAL: Timer1 Gate Current State bit (Read only)
    '00 = Timer1 gate pin
    T1GCON = %11110000
   
    '10 = Timer1 clock source is the T1OSC or T1CKI pin
    '00 = 1:1 Prescale value
    '0 = Timer1 crystal driver is off, Timer1 clock is from the T1CKI input pin
    '0 = Synchronize external clock input
    '1 = Enables register read/write of Timer1 in one 16-bit operation
    '0 = Stops Timer1
    T1CON = %10000010

   
    'Clear TMR1 interrupt flag
    TMR1IF = 0
   
    'Enables the TMR1 overflow interrupt
    PIE1.0 = 1

    'Global Interrupt Enable bit
    'Peripheral/Low-Priority Interrupt Enable bit
    INTCON = %11000000
   
    'Reset timer and overflow counter
    wTimer1 = 0
    wTMR1Overflow = 0
   
    'Start Timer1
    TMR1ON = 1
    
    'T1GGO = Timer1 gate single pulse acquisition is ready, waiting for an edge  
    T1GGO = 1 
EndProc  

Proc SetPPS()
    'Unlock the PPS
    EECON2 = $55
    EECON2 = $AA
    PPSCON = 0
    'T1G to RP12
    RPINR12 = %00001100 
EndProc    
       

[david]

Hi,
The 1pps timing signal typically has a jitter of around 30nS RMS (mainly atmospheric induced) which is considered excessive (for telco apps) so is often integrated over several minutes to provide a sub-nanosecond reference stability.  For radio applications as described the approach taken is quite sufficient.
I've used the CCP module to count out 16  one second intervals and then capture a snapshot of the Tmr1 counter.  It's critical to never reset the main counter as fractional counts are rounded down and lost.
It's also generally unnecessary to count the overflows due to the stability of the clock and all that is really required is the value of the last partial count.
For example a 10MHz clock source will overflow a 16 bit counter 152 times in 1 second and have a remainder count of 38680 counts.   Even for a shoddy TCXO of say +/-2ppm that remainder count will only vary by +/-20 counts so you can forget the 152 overflows and just use this error count to control the TCXO.  If the count is > than ideal count the clock is fast and if it's < then it's slow and the voltage control pin of the TCXO can be used to correct any offset.   Some PICs have 16 bit PWM modules with internal clocks of 64MHz which allows a 16 bit DAC to be realised with a 1kHz carrier that can be filtered as a control voltage.  If using pwm then the voltage supply of the device also needs to be well regulated as the DC level of the pwm is the integral of the amplitude and duty cycle.
For ublox GPS modules the timing pulse is configurable via the proprietary ubx messages and extends from 0.25Hz to several MHz.

Cheers,
David

[John Drew]

Silicon Chip magazine produced a GPS disciplined oscillator based frequency counter. It largely overcomes the jitter mentioned by David to provide improved accuracy over using the 1pps as the gate.

I reprogammed the PIC for a friend to change the baud rate of the data stream as the project also had a UTC clock function and his GPS had a different baud rate. Proton to the rescue with a new program.
John

[JonW]

So true, most GPS module clock sources that I have tested have poor jitter/phase noise, but can be cleaned up easily with some of the Silabs jitter attenuators.  I use these in a Tri or Quad PLL reference loops to GPS lock and phase synchronize VCO's and test kit to beyond 30GHz+.

[John Drew]

So true, most GPS module clock sources that I have tested have poor jitter/phase noise, but can be cleaned up easily with some of the Silabs jitter attenuators.  I use these in a Tri or Quad PLL reference loops to GPS lock and phase synchronize VCO's and test kit to beyond 30GHz+.

I didn't know about those Jon. So for a frequency counter you'd GPS lock a crystal e.g. 10MHz then de-jitter the 10MHz output? Which of their many devices did you use?
Any chance of a hand drawn block diagram of the oscillator section?
John

[david]

John - I've used the Si5340 chips which are rated <100fS but these are multi-output PLLs with almost every parameter adjustable - including the relative phase of the differential outputs.  They would be an overkill if you just want a single reference clock.
For a shack frequency counter, close in phase noise is not critical and a TCXO will suffice provided it's protected against airflow.(on-chip temperature sensor and xtal resonator have different lag rates)   TCXOs generally use an AT cut xtal and a small ASIC which generates analog compensation functions (1st, 3rd, 4th order...) that are summed to flatten the almost sine like temperature response of the AT cut xtal.  Adding multiple analog functions produces increased close-in phase noise and for more critical applications a good ovenised xtal oscillator is much preferred.
The GPS timing jitter can be overcome by longer integration times but this has to be somewhat matched to the short-medium term stability of the oscillator used - there's no point in having a 15 minute integration time if the oscillator has gone off track in two minutes.  Also beware of cheap ex telco 10MHz reference modules - some will have aged to almost the limit of their control range and leave you almost nothing to compensate with. 

Cheers,
David

[JonW]

David is accurate. We use clean up loops for high data throughput and any frequency multiplication can (not always depending on phase) degrade the noise within the loop bandwidth to an approximate (20logN + Noise + (Interference), thus noise is integrated (RMS)) versus frequency (can approximate using the trapezoid function) over the full comms channel BW.  I use the silabs devices for the simple fact that building a loop filter to sub hertz BW cannot be realised easily in the analog domain and to achieve high MER over the comms link you cannot simply rely on the IDU (Modem) for a super low phase noise reference, especially multiplying to >>GHz range, hence you need to use fractional loop bandwidths for phase sync. . However you can use the Silabs chips in the most basic of loops with little code overhead and will cost < $5, it doesn't have to be complex, and we use one loop in the silabs devices and close other loops with higher frequencies to ensure we get the best cross over of 1/f, FOM of logic noise floor, open loop phase noise of the VCO and reference noise.  Again as David states build a low noise oscillator using a 10c xtal.  You can hit -155dBc/Hc at 1K offset easy for less than 20 cents of parts.  Keep this at a constant temp >> room temp using a reg and a current sink from MCU and you will have a great stable source. 

John i know you want stable sources at higher offsets locked to a standard.. Then these devices are very well suited to these applications.  AKA Leo Bodnar type sources, they use the Silabs asics.... These use the same Asics to produce any clock from any source and use a backup source (tcxo) in the main pll if the gps  loses lock.  Sounds complex but its really basic.  They are infinitely adjustable but don't be put off, < 4k of code space and a reasonable host TCXO and you can lock up any crappy signal and blow the loop out to achieve a fast lock then narrow the BW over time for stability. I use a UBLOX M8 module locked to multiple constellations and then sub lock.  (2 chips plus MCU and TCXO) (Almost same as Leo Bodnar (but we sub lock to get a better RMS result for a higher reference (remembering the reference phase nose is multiplied (in loop)  by 20 Log N))).  I take this much further but its not required for a simple lock.  Its power is in the any frequency lock ability with the dividers and programmable  loop bw.

These are good low cost no frills VCTCXO, https://www.mouser.com/datasheet/2/3/ABLNO-1774945.pdf.  You can frequency steer with PWM easily and frequency lock(time based).   I used the same principle in the famous Bullseye LNB I designed.
 An upgrade from the standard universal we produce.  In this case it was a side project to decode very narrow band sat channels for Othernet using Lora over Satellite bullseye
This uses a similar tech with  the most basic 10C VCTCXO (but well researched) and some fancy code to hit 100hz at 10G with calibration and time based approximation of drift taken by cycling and measuring over 5k TCXO, over 50 batches, over temperature -40C to 85C and building data looking at CPK and creating a simple curve fitting algorithm (not perfect as time, mech relaxation and pressure  cant be approximated). Thus , I also built a user recalibration by serial comms for production calibration when sealed but later released to public to maintain accuracy, I released the protocol (Guy called Colin from British amateur Radio made an aduino based recal tool).  The LNB  uses a basic $0.03 8 Bit Chinese MCU coded in ASM to hold the loops stable and provide control and calibration algorithms. Tried to get a GPS (kind of) reference stability for pence, massive design challenge considering i had 3 weeks to develop it at a cost of << $0.10 over a standard LNB for only 10k build

Epson have some really low jitter TCXO sub $1 that can put many of the stand alone TCXO to bed with 30dB in the pocket (-155 @1K) if you know what to look for.

Lora is an amazing tech if you understand complex  noise.... It can coexist (depending on KTB)  without degradation on both comms channels.  Basically in the satellite world with a good low noise  lnb, with a decent feed horn (bullseye)  you can close the loop with LNB to SAT at 10kb/s 'without a dish' 36km from earth to a Geo satellite on a <<5kHz channel  (modulation dependant), where lora is 20dB below the normalized satellite noise floor (Say noise floor as this is NOT KTB noise floor) hence lora can be recovered.: Pretty cool tech.  Puts the 10 - 50km Lora ground based comms to shame (Granted they don't have COLD sky and limited G/T)

John. Used a Si5328.  worked the math in Excel at first and looked up constants in flash memory (you can easy do this).  Then produced computed variables in MCU but this has a massive code overhead for dialled in output frequencies. for all the pre/post/VCO sub dividers. plus you need to reprogram the GPS clock to minimise Jitter.  Forgive me but i can release the code for this.

[John Drew]

Jon: Thanks for the detail. It's well beyond my knowledge but you've given me some homework to learn more.
I appreciate your taking the time to explain how it works.
No need for the code, it's my curiosity at work. I have an HP frequency meter that is adequate for my tasks.
Cheers
John

[HAL]

A few years back ebay had for sale, board mounted GPS chips from UBLOX known as the LEA-6T which are designed with timing and frequency as their primary function.  The boards were reasonably priced at $30US.  These LEA-6T modules can be configured to produce a pulse/frequency output from 1PPS to 10Megahertz.  The small problem is that the 10MHz output had an incredible amount of jitter. However, it seemed the jitter was a consequence of the  NCO (Numerically Controlled Oscillator) and phase accumulator used to derive the clock output from the GPS receiver's clock.  Apparently, the NCO provides jitter as a consequence of a divide of its GPS receiver's 48MHz clock with a divisor which leaves a remainder.  The clock pulse cleans up nicely if the 48MHz is divided evenly by 4, 6, or 8 as examples.  I believe I used 6 as a divisor which gave a fairly clean output of 8MHz.  This 8MHz was sent to a PLL / multiplier chip PT7C4511 (sold by DigiKey) https://www.digikey.com/en/products/detail/diodes-incorporated/PT7C4511WEX/6237508  which can take an external input of 1 to 50 MHZ and produce a multiplied output of 9 possible values.  I used 5 times 8 and then divided the 40MHz result by 4 to provide a 10MHz output with a 50% duty cycle.  I use the output for a counter which has a 10MHz input for an external time base.    UBLOX :    https://www.u-blox.com/en/positioning-chips-and-modules    is an excellent source of information on their products as well as GNSS / GPS in general.    LEA-6T:  https://content.u-blox.com/sites/default/files/products/documents/LEA-NEO-6T_ProductSummary_%28UBX-13003351%29.pdf    Ebay has some at search:  Ublox LEA-6T-0-001 timing GPS module EVK BOARD 
and I believe they have 7 boards left at about $37 +shipping.

Best regards
HAL

[trastikata]

As david said, for RF radio it is sufficiently precise, but I did not mean to show the hardware, rather the code.

The purpose of this post was to show the code using entirely hardware based triggers for Timer1 and the code simplicity of a frequency counter by using this approach instead of a Firmware Interrupt driven pin...