12F1840 Configuration issue

[shantanu@india]

Hi,
The following configuration(set by PIC Fuse Configurator Mk2):

Code Select Expand

Config1 FOSC_INTOSC, WDTE_ON, PWRTE_ON, MCLRE_OFF, CP_ON, CPD_ON, BOREN_ON, CLKOUTEN_OFF, IESO_OFF, FCMEN_OFF
Config2 WRT_OFF, PLLEN_OFF, STVREN_ON, BORV_LO, LVP_OFF
is generating the error "Error in device info section of PPI file"
In the PPI file I found the setting as BORV_19 or BORV_25 for low(1.9V) & high(2.5V) respectively.
Maybe there are some compatibility issues with MPASM.
Any pointers please?

[Maxi]

Here is my working config

Code Select Expand

Device = 12F1840
Config1 FOSC_INTOSC, WDTE_OFF, PWRTE_ON, MCLRE_OFF, CP_ON, CPD_ON, BOREN_OFF, CLKOUTEN_OFF, IESO_OFF, FCMEN_OFF
Config2 WRT_OFF, PLLEN_OFF, STVREN_OFF, BORV_19, LVP_OFF
Declare Xtal=8


[shantanu@india]

Thanks. I'll try this

[Stephen Moss]

In the PPI file I found the setting as BORV_19 or BORV_25 for low(1.9V) & high(2.5V) respectively.
Maybe there are some compatibility issues with MPASM.
Any pointers please?

Set the fuse configurator to generate its output in assembler, that gets around any fuse name mismatches between those the compiler uses and those Microchip use (usually the result of Microchip changing them after the PPI files were created).

[top204]

Microchip constantly change the names of SFRs and fuse settings in their datasheets and other info files etc, so when the compiler's PPI files are created, the compiler can only use those names that microchip chose to use then. The PIC12F1840's .ppi file was created in 2010 (see the top of the ppi file), so it is guaranteed that microchip will have changed some name or other since then. They just cannot help themselves. :-)

Therefore always look in the device's .ppi file for valid fuse names. For example, in the "P12F1840.ppi" file, the valid config fuses are:

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Fuse Name Definitions
[CONFIGSTART]
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1 EQU 0X8007
_CONFIG2 EQU 0X8008
; _CONFIG1 Options
FOSC_LP EQU 0XFFF8 ; LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins
FOSC_XT EQU 0XFFF9 ; XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins
FOSC_HS EQU 0XFFFA ; HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins
FOSC_EXTRC EQU 0XFFFB ; EXTRC oscillator: External RC circuit connected to CLKIN pin
FOSC_INTOSC EQU 0XFFFC ; INTOSC oscillator: I/O function on CLKIN pin
FOSC_ECL EQU 0XFFFD ; ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pin
FOSC_ECM EQU 0XFFFE ; ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pin
FOSC_ECH EQU 0XFFFF ; ECH, External Clock, High Power Mode (4-32 MHz): device clock supplied to CLKIN pin
WDTE_OFF EQU 0XFFE7 ; WDT disabled
WDTE_SWDTEN EQU 0XFFEF ; WDT controlled by the SWDTEN bit in the WDTCON register
WDTE_NSLEEP EQU 0XFFF7 ; WDT enabled while running and disabled in Sleep
WDTE_ON EQU 0XFFFF ; WDT enabled
PWRTE_ON EQU 0XFFDF ; PWRT enabled
PWRTE_OFF EQU 0XFFFF ; PWRT disabled
MCLRE_OFF EQU 0XFFBF ; MCLR/VPP pin function is digital input
MCLRE_ON EQU 0XFFFF ; MCLR/VPP pin function is MCLR
CP_ON EQU 0XFF7F ; Program memory code protection is enabled
CP_OFF EQU 0XFFFF ; Program memory code protection is disabled
CPD_ON EQU 0XFEFF ; Data memory code protection is enabled
CPD_OFF EQU 0XFFFF ; Data memory code protection is disabled
BOREN_OFF EQU 0XF9FF ; Brown-out Reset disabled
BOREN_SBODEN EQU 0XFBFF ; Brown-out Reset controlled by the SBOREN bit in the BORCON register
BOREN_NSLEEP EQU 0XFDFF ; Brown-out Reset enabled while running and disabled in Sleep
BOREN_ON EQU 0XFFFF ; Brown-out Reset enabled
CLKOUTEN_ON EQU 0XF7FF ; CLKOUT function is enabled on the CLKOUT pin
CLKOUTEN_OFF EQU 0XFFFF ; CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin
IESO_OFF EQU 0XEFFF ; Internal/External Switchover mode is disabled
IESO_ON EQU 0XFFFF ; Internal/External Switchover mode is enabled
FCMEN_OFF EQU 0XDFFF ; Fail-Safe Clock Monitor is disabled
FCMEN_ON EQU 0XFFFF ; Fail-Safe Clock Monitor is enabled
; _CONFIG2 Options
WRT_ALL EQU 0XFFFC ; 000h to FFFh write protected, no addresses may be modified by EECON control
WRT_HALF EQU 0XFFFD ; 000h to 7FFh write protected, 800h to FFFh may be modified by EECON control
WRT_BOOT EQU 0XFFFE ; 000h to 1FFh write protected, 200h to FFFh may be modified by EECON control
WRT_OFF EQU 0XFFFF ; Write protection off
PLLEN_OFF EQU 0XFEFF ; 4x PLL disabled
PLLEN_ON EQU 0XFFFF ; 4x PLL enabled
STVREN_OFF EQU 0XFDFF ; Stack Overflow or Underflow will not cause a Reset
STVREN_ON EQU 0XFFFF ; Stack Overflow or Underflow will cause a Reset
BORV_25 EQU 0XFBFF ; Brown-out Reset Voltage (VBOR) set to 2.5 V
BORV_19 EQU 0XFFFF ; Brown-out Reset Voltage (VBOR) set to 1.9 V
LVP_OFF EQU 0XDFFF ; High-voltage on MCLR/VPP must be used for programming
LVP_ON EQU 0XFFFF ; Low-voltage programming enabled
; DEVID Equates
DEVID1 EQU 0X8006
; IDLOC Equates
IDLOC0 EQU 0X8000
IDLOC1 EQU 0X8001
IDLOC2 EQU 0X8002
IDLOC3 EQU 0X8003
[CONFIGEND]

The compiler's ppi files can be found here: "C:\Program Files (x86)\ProtonIDE\PDS\Includes\PPI\"

In your original code, microchip have changed the original name of BORV_19 to BORV_LO. So your config setup will be:

Code Select Expand

    Config1 FOSC_INTOSC, WDTE_ON, PWRTE_ON, MCLRE_OFF, CP_ON, CPD_ON, BOREN_ON, CLKOUTEN_OFF, IESO_OFF, FCMEN_OFF
    Config2 WRT_OFF, PLLEN_OFF, STVREN_ON, BORV_19, LVP_OFF

An incorrect fuse name will cause the assembler to give an "Invalid Fuse Setting [fuse name]" error, so then go into the device's .ppi file and see what the valid fuse names are, and change it in the program listing's configs.

Never change the contents of a .ppi file, unless absolutely necessary, or instructed to do so and with what. Because this may cause the compiler to not be able to parse its contents. The .ppi file is meant for the compiler to read and parse, so it has strict rules on its contents and formatting.