PIC18F Timer1 Hardware set-up logic?

[trastikata]

Hello,

I work on a project where I am a bit stuck and can't think of a hardware combination ...

- Timer1 is clocked from an external clock
- Timer1 overflows also have to be counted
- At some random moment an external signal (hardware interrupt / gate) will ask a snapshot of the current Timer1 counter and overflows
- Another external signal (hardware interrupt / gate) will trigger Timer1 counter and overflow reset

I am aware this can be easily done inside interrupt routines but all this has to be done without loosing any clock counts or resets from the external sources - thus I am looking to implement it with hardware triggers only or as much as possible.

Timer1 gate pin function is perfect but I can't find a way to use it as reset for the timer like a Special Event Trigger could reset. 

Any ideas would be appreciated.

[keytapper]

The timer(s) cannot be reset from the hardware. There's the only option to do it from the software. That might be an interrupt from external sources and one instruction cycle to reset the timer. AFAIK.

[Stephen Moss]

As Keytapper said, if there is no internal hardware solution in the PIC for clearing the clock it will have to be done via software interrupt, which is usually the case.

If there is a timer 1 gate pin interrupt you may be able to use that to trigger the reset interrupt without it actually gating the clock to the timer although whether or not that is possible would depend on the setup of the PIC in question.

As for not missing any Timer clock pulses during the reset whether or not that will be a problem will depend on the difference between its frequency and how long it takes to reset the counter and overflow counts. For example...

• If you have a 20MHZ clock (4MHz instruction clock) and a 10MHz clock in to Timer 1 then you will have to calculate how many timer clocks would be missed during the reset and write that value to the TMR register to compensate rather than 0 when "clearing" the timer.
• If you have an 80MHz clock for the PIC and 5MHz clock for the timer the instruction cycle should be fast enough that you can reset between timer clock inputs and so none will be missed and no compensation value will need to be written to the Timer and it can be cleared to 0.

   

[TimB]

Probably off the exact topic but what you can do to cover the timer issue ref reloading is to (if I remember right) add the current Tmr1 to the reload value then put that in the tmr

Tmr1 = Tmr1+TmrRelaod

Also remember that some timers can be read and written to in 1 cycle.

[John Lawton]

Probably off the exact topic but what you can do to cover the timer issue ref reloading is to (if I remember right) add the current Tmr1 to the reload value then put that in the tmr

Tmr1 = Tmr1+TmrRelaod

Also remember that some timers can be read and written to in 1 cycle.

Cunning, I like that

[tumbleweed]

Tmr1 = Tmr1+TmrReload

Also remember that some timers can be read and written to in 1 cycle.

On a PIC18, assuming TmrReload is a const that can take 4-5 cycles with the timer in 8-bit read mode  (TxCON.RD16=0) so there can be problems since there may be a carry-out of TMRxL to TMRxH in between the individual byte reads and the addition. If it's a variable it can be worse... upwards of 8 cycles if banking is involved.

Setting the timer to 16-bit read/write mode (RD16=1) allows you to latch TMRxH when TMRxL is read to avoid the carry issues, but when you write it in 16-bit mode it must be done TMRxH then TMRxL, and the expression "Tmr1 = Tmr1+TmrReload" doesn't do that... it reads/adds TMRL then it reads/adds TMRxH.

In some special cases "it works", but in the general case you have to read the TMR into a variable, add, then write it back in the correct order.


I think trastikata only really needs to reset the timer for his application, so that's a bit easier.

FWIW, some of the PIC18 devices have a UTMR Universal Timer module that allows you to chain two 16-bit timers to create a 32-bit counter, and have an external reset input along with the usual gate controls, etc.

Unfortunately, it's only in the 18FxxQ83, 18FxxQ84, and 18FxxQ71, none of which are currently supported.
 

[trastikata]

Thank you all for the reply.

I was hoping that there might be something I miss and can route the signal using different in and out pins to reset the counter as in Compare Mode for the ECCP module, which supports hardware reset, but ONLY in Compare and not in Capture mode.

A seamless reset without loosing external clock counts would have been perfect, but I'd have to do it in ISR and preset the counter for the lost number of clocks (6.5 MHz) at pin T1CKI.

[Giuseppe MPO]

You can try to see if it is possible to concatenate two 16bit TIMERS in hardware using the functions offered by the PPS to have one 32bit. This way you don't waste clock cycles

[Giuseppe MPO]

sorry, I forgot to say, also using the CLC. combining CLC, TIMER and PPS could achieve the purpose.