18F25K22 config

[See_Mos]

Help please,  I am overheating and so is my PIC!

Does anyone have a working config etc for external 16MHz XTAL with PLL to 64MHz ?

I am working on some code with critical timing but the outcome is all over the place and not as calculated.  A quick squirt from the freezer can restored near normal operation.

No problem I thought, switch to an external crystal but I haven't been able to get it working.  I tried setting CONFIG1H as shown in the data sheet but the register is not recognized by the compiler.

[top204]

The CONFIG fuses became obsolete with 18F device quite a few years ago, and are now not valid at all in some of the newer types. Instead, they use a much better system, as shown below:

Code Select Expand

    Device = 18F25K22
    Declare Xtal = 64

'----------------------------------------------------------------------------------------------
' Set the config fuses for a PIC18F25K22 device to operate at 64MHz with an external 16MHz crystal
'
Config_Start
    FOSC = HSHP           ' HS oscillator (high power > 16 MHz)
    PLLCFG = On           ' Oscillator multiplied by 4
    PRICLKEN = On         ' Primary clock enabled
    FCMEN = Off           ' Fail-Safe Clock Monitor disabled
    IESO = Off            ' Internal/External Oscillator Switchover mode disabled
    PWRTEN = On           ' Power up timer enabled
    BOREN = SBORDIS       ' Brown-out Reset enabled in hardware only (SBOREN is disabled)
    BORV = 190            ' Brown Out Reset Voltage set to 1.90 V nominal
    WDTEN = Off           ' Watch dog timer is always disabled. SWDTEN has no effect.
    WDTPS = 128           ' Watchdog Timer Postscale 1:128
    CCP2MX = PORTC1       ' CCP2 input/output is multiplexed with RC1
    PBADEN = Off          ' PORTB<5:0> pins are configured as digital I/O on Reset
    CCP3MX = PORTB5       ' P3A/CCP3 input/output is multiplexed with RB5
    HFOFST = On           ' HFINTOSC output and ready status are not delayed by the oscillator stable status
    T3CMX = PORTC0        ' Timer3 Clock Input (T3CKI) is on RC0
    P2BMX = PORTB5        ' ECCP2 B (P2B) is on RB5
    MCLRE = EXTMCLR       ' MCLR pin enabled, RE3 input pin disabled
    STVREN = Off          ' Stack full/underflow will not cause Reset
    LVP = Off             ' Single-Supply ICSP disabled
    XINST = Off           ' Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
    Debug = Off           ' Disabled
    Cp0 = Off             ' Block 0 (000800-001FFF) not code-protected
    CP1 = Off             ' Block 1 (002000-003FFF) not code-protected
    CP2 = Off             ' Block 2 (004000-005FFF) not code-protected
    CP3 = Off             ' Block 3 (006000-007FFF) not code-protected
    CPB = Off             ' Boot block (000000-0007FF) not code-protected
    CPD = Off             ' Data EEPROM not code-protected
    WRT0 = Off            ' Block 0 (000800-001FFF) not write-protected
    WRT1 = Off            ' Block 1 (002000-003FFF) not write-protected
    WRT2 = Off            ' Block 2 (004000-005FFF) not write-protected
    WRT3 = Off            ' Block 3 (006000-007FFF) not write-protected
    WRTC = Off            ' Configuration registers (300000-3000FF) not write-protected
    WRTB = Off            ' Boot Block (000000-0007FF) not write-protected
    WRTD = Off            ' Data EEPROM not write-protected
    EBTR0 = Off           ' Block 0 (000800-001FFF) not protected from table reads executed in other blocks
    EBTR1 = Off           ' Block 1 (002000-003FFF) not protected from table reads executed in other blocks
    EBTR2 = Off           ' Block 2 (004000-005FFF) not protected from table reads executed in other blocks
    EBTR3 = Off           ' Block 3 (006000-007FFF) not protected from table reads executed in other blocks
    EBTRB = Off           ' Boot Block (000000-0007FF) not protected from table reads executed in other blocks
Config_End

The fuses for the devices are listed at the bottom of a device's .ppi file, with explanations beside them.

For example, at the bottom of the PIC18F25K22 device's .ppi file, there is:

Code Select Expand

Fuse Definitions
[FUSESTART]
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive.  The following settings
; are available for this device.
; Oscillator Selection Bits:
FOSC=LP        ; LP oscillator
FOSC=XT        ; XT oscillator
FOSC=HSHP        ; HS oscillator (high power > 16 MHz)
FOSC=HSMP        ; HS oscillator (medium power 4-16 MHz)
FOSC=ECHP        ; EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz)
FOSC=ECHPIO6        ; EC oscillator, port function on RA6 (high power, >16 MHz)
FOSC=RC        ; External RC, CLKOUT on OSC2
FOSC=RCIO6        ; External RC oscillator, port function on RA6
FOSC=INTIO67        ; Internal oscillator block, port function on RA6 and RA7
FOSC=INTIO7        ; Internal oscillator block, CLKOUT function on RA6, port function on RA7
FOSC=ECMP        ; EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz)
FOSC=ECMPIO6        ; EC oscillator (medium power, 4-16 MHz)
FOSC=ECLP        ; EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz)
FOSC=ECLPIO6        ; EC oscillator  (low power, < 4 MHz)
; 4X PLL Enable:
PLLCFG=OFF        ; Oscillator used directly
PLLCFG=ON        ; Oscillator multiplied by 4
; Primary clock enable bit:
PRICLKEN=OFF        ; Primary clock can be disabled by software
PRICLKEN=ON        ; Primary clock enabled
; Fail-Safe Clock Monitor Enable bit:
FCMEN=OFF        ; Fail-Safe Clock Monitor disabled
FCMEN=ON        ; Fail-Safe Clock Monitor enabled
; Internal/External Oscillator Switchover bit:
IESO=OFF        ; Oscillator Switchover mode disabled
IESO=ON        ; Oscillator Switchover mode enabled
; Power-up Timer Enable bit:
PWRTEN=ON        ; Power up timer enabled
PWRTEN=OFF        ; Power up timer disabled
; Brown-out Reset Enable Bits:
BOREN=OFF        ; Brown-out Reset disabled in hardware and software
BOREN=ON        ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN=NOSLP        ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
BOREN=SBORDIS        ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
; Brown Out Reset Voltage Bits:
BORV=285        ; VBOR set to 2.85 V nominal
BORV=250        ; VBOR set to 2.50 V nominal
BORV=220        ; VBOR set to 2.20 V nominal
BORV=190        ; VBOR set to 1.90 V nominal
; Watchdog Timer Enable Bits:
WDTEN=OFF        ; Watch dog timer is always disabled. SWDTEN has no effect.
WDTEN=NOSLP        ; WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect
WDTEN=SWON        ; WDT is controlled by SWDTEN bit of the WDTCON register
WDTEN=ON        ; WDT is always enabled. SWDTEN bit has no effect
; Watchdog Timer Postscale Select Bits:
WDTPS=1        ; 1:1
WDTPS=2        ; 1:2
WDTPS=4        ; 1:4
WDTPS=8        ; 1:8
WDTPS=16        ; 1:16
WDTPS=32        ; 1:32
WDTPS=64        ; 1:64
WDTPS=128        ; 1:128
WDTPS=256        ; 1:256
WDTPS=512        ; 1:512
WDTPS=1024        ; 1:1024
WDTPS=2048        ; 1:2048
WDTPS=4096        ; 1:4096
WDTPS=8192        ; 1:8192
WDTPS=16384        ; 1:16384
WDTPS=32768        ; 1:32768
; CCP2 MUX bit:
CCP2MX=PORTB3        ; CCP2 input/output is multiplexed with RB3
CCP2MX=PORTC1        ; CCP2 input/output is multiplexed with RC1
; PORTB A/D Enable bit:
PBADEN=OFF        ; PORTB<5:0> pins are configured as digital I/O on Reset
PBADEN=ON        ; PORTB<5:0> pins are configured as analog input channels on Reset
; P3A/CCP3 Mux bit:
CCP3MX=PORTC6        ; P3A/CCP3 input/output is mulitplexed with RC6
CCP3MX=PORTB5        ; P3A/CCP3 input/output is multiplexed with RB5
; HFINTOSC Fast Start-up:
HFOFST=OFF        ; HFINTOSC output and ready status are delayed by the oscillator stable status
HFOFST=ON        ; HFINTOSC output and ready status are not delayed by the oscillator stable status
; Timer3 Clock input mux bit:
T3CMX=PORTB5        ; T3CKI is on RB5
T3CMX=PORTC0        ; T3CKI is on RC0
; ECCP2 B output mux bit:
P2BMX=PORTC0        ; P2B is on RC0
P2BMX=PORTB5        ; P2B is on RB5
; MCLR Pin Enable bit:
MCLRE=INTMCLR        ; RE3 input pin enabled; MCLR disabled
MCLRE=EXTMCLR        ; MCLR pin enabled, RE3 input pin disabled
; Stack Full/Underflow Reset Enable bit:
STVREN=OFF        ; Stack full/underflow will not cause Reset
STVREN=ON        ; Stack full/underflow will cause Reset
; Single-Supply ICSP Enable bit:
LVP=OFF        ; Single-Supply ICSP disabled
LVP=ON        ; Single-Supply ICSP enabled if MCLRE is also 1
; Extended Instruction Set Enable bit:
XINST=OFF        ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST=ON        ; Instruction set extension and Indexed Addressing mode enabled
; Background Debug:
DEBUG=ON        ; Enabled
DEBUG=OFF        ; Disabled
; Code Protection Block 0:
CP0=ON        ; Block 0 (000800-001FFFh) code-protected
CP0=OFF        ; Block 0 (000800-001FFFh) not code-protected
; Code Protection Block 1:
CP1=ON        ; Block 1 (002000-003FFFh) code-protected
CP1=OFF        ; Block 1 (002000-003FFFh) not code-protected
; Code Protection Block 2:
CP2=ON        ; Block 2 (004000-005FFFh) code-protected
CP2=OFF        ; Block 2 (004000-005FFFh) not code-protected
; Code Protection Block 3:
CP3=ON        ; Block 3 (006000-007FFFh) code-protected
CP3=OFF        ; Block 3 (006000-007FFFh) not code-protected
; Boot Block Code Protection bit:
CPB=ON        ; Boot block (000000-0007FFh) code-protected
CPB=OFF        ; Boot block (000000-0007FFh) not code-protected
; Data EEPROM Code Protection bit:
CPD=ON        ; Data EEPROM code-protected
CPD=OFF        ; Data EEPROM not code-protected
; Write Protection Block 0:
WRT0=ON        ; Block 0 (000800-001FFFh) write-protected
WRT0=OFF        ; Block 0 (000800-001FFFh) not write-protected
; Write Protection Block 1:
WRT1=ON        ; Block 1 (002000-003FFFh) write-protected
WRT1=OFF        ; Block 1 (002000-003FFFh) not write-protected
; Write Protection Block 2:
WRT2=ON        ; Block 2 (004000-005FFFh) write-protected
WRT2=OFF        ; Block 2 (004000-005FFFh) not write-protected
; Write Protection Block 3:
WRT3=ON        ; Block 3 (006000-007FFFh) write-protected
WRT3=OFF        ; Block 3 (006000-007FFFh) not write-protected
; Configuration Register Write Protection bit:
WRTC=ON        ; Configuration registers (300000-3000FFh) write-protected
WRTC=OFF        ; Configuration registers (300000-3000FFh) not write-protected
; Boot Block Write Protection bit:
WRTB=ON        ; Boot Block (000000-0007FFh) write-protected
WRTB=OFF        ; Boot Block (000000-0007FFh) not write-protected
; Data EEPROM Write Protection bit:
WRTD=ON        ; Data EEPROM write-protected
WRTD=OFF        ; Data EEPROM not write-protected
; Table Read Protection Block 0:
EBTR0=ON        ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0=OFF        ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
; Table Read Protection Block 1:
EBTR1=ON        ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1=OFF        ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
; Table Read Protection Block 2:
EBTR2=ON        ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2=OFF        ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
; Table Read Protection Block 3:
EBTR3=ON        ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3=OFF        ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
; Boot Block Table Read Protection bit:
EBTRB=ON        ; Boot Block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB=OFF        ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
[FUSEEND]

Fuse Name Definitions
[CONFIGSTART]
CONFIG1H EQU 0X300001
CONFIG2L EQU 0X300002
CONFIG2H EQU 0X300003
CONFIG3H EQU 0X300005
CONFIG4L EQU 0X300006
CONFIG5L EQU 0X300008
CONFIG5H EQU 0X300009
CONFIG6L EQU 0X30000A
CONFIG6H EQU 0X30000B
CONFIG7L EQU 0X30000C
CONFIG7H EQU 0X30000D
; CONFIG1H Options
FOSC_LP_1 EQU 0XF0 ; LP oscillator
FOSC_XT_1 EQU 0XF1 ; XT oscillator
FOSC_HSHP_1 EQU 0XF2 ; HS oscillator (high power > 16 MHz)
FOSC_HSMP_1 EQU 0XF3 ; HS oscillator (medium power 4-16 MHz)
FOSC_ECHP_1 EQU 0XF4 ; EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz)
FOSC_ECHPIO6_1 EQU 0XF5 ; EC oscillator, port function on RA6 (high power, >16 MHz)
FOSC_RC_1 EQU 0XF6 ; External RC, CLKOUT on OSC2
FOSC_RCIO6_1 EQU 0XF7 ; External RC oscillator, port function on RA6
FOSC_INTIO67_1 EQU 0XF8 ; Internal oscillator block, port function on RA6 and RA7
FOSC_INTIO7_1 EQU 0XF9 ; Internal oscillator block, CLKOUT function on RA6, port function on RA7
FOSC_ECMP_1 EQU 0XFA ; EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz)
FOSC_ECMPIO6_1 EQU 0XFB ; EC oscillator (medium power, 4-16 MHz)
FOSC_ECLP_1 EQU 0XFC ; EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz)
FOSC_ECLPIO6_1 EQU 0XFD ; EC oscillator (low power, < 4 MHz)
PLLCFG_OFF_1 EQU 0XEF ; Oscillator used directly
PLLCFG_ON_1 EQU 0XFF ; Oscillator multiplied by 4
PRICLKEN_OFF_1 EQU 0XDF ; Primary clock can be disabled by software
PRICLKEN_ON_1 EQU 0XFF ; Primary clock enabled
FCMEN_OFF_1 EQU 0XBF ; Fail-Safe Clock Monitor disabled
FCMEN_ON_1 EQU 0XFF ; Fail-Safe Clock Monitor enabled
IESO_OFF_1 EQU 0X7F ; Oscillator Switchover mode disabled
IESO_ON_1 EQU 0XFF ; Oscillator Switchover mode enabled
; CONFIG2L Options
PWRTEN_ON_2 EQU 0XFE ; Power up timer enabled
PWRTEN_OFF_2 EQU 0XFF ; Power up timer disabled
BOREN_OFF_2 EQU 0XF9 ; Brown-out Reset disabled in hardware and software
BOREN_ON_2 EQU 0XFB ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
BOREN_NOSLP_2 EQU 0XFD ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
BOREN_SBORDIS_2 EQU 0XFF ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV_285_2 EQU 0XE7 ; VBOR set to 2.85 V nominal
BORV_250_2 EQU 0XEF ; VBOR set to 2.50 V nominal
BORV_220_2 EQU 0XF7 ; VBOR set to 2.20 V nominal
BORV_190_2 EQU 0XFF ; VBOR set to 1.90 V nominal
; CONFIG2H Options
WDTEN_OFF_2 EQU 0XFC ; Watch dog timer is always disabled. SWDTEN has no effect.
WDTEN_NOSLP_2 EQU 0XFD ; WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect
WDTEN_SWON_2 EQU 0XFE ; WDT is controlled by SWDTEN bit of the WDTCON register
WDTEN_ON_2 EQU 0XFF ; WDT is always enabled. SWDTEN bit has no effect
WDTPS_1_2 EQU 0XC3 ; 1:1
WDTPS_2_2 EQU 0XC7 ; 1:2
WDTPS_4_2 EQU 0XCB ; 1:4
WDTPS_8_2 EQU 0XCF ; 1:8
WDTPS_16_2 EQU 0XD3 ; 1:16
WDTPS_32_2 EQU 0XD7 ; 1:32
WDTPS_64_2 EQU 0XDB ; 1:64
WDTPS_128_2 EQU 0XDF ; 1:128
WDTPS_256_2 EQU 0XE3 ; 1:256
WDTPS_512_2 EQU 0XE7 ; 1:512
WDTPS_1024_2 EQU 0XEB ; 1:1024
WDTPS_2048_2 EQU 0XEF ; 1:2048
WDTPS_4096_2 EQU 0XF3 ; 1:4096
WDTPS_8192_2 EQU 0XF7 ; 1:8192
WDTPS_16384_2 EQU 0XFB ; 1:16384
WDTPS_32768_2 EQU 0XFF ; 1:32768
; CONFIG3H Options
CCP2MX_PORTB3_3 EQU 0XFE ; CCP2 input/output is multiplexed with RB3
CCP2MX_PORTC1_3 EQU 0XFF ; CCP2 input/output is multiplexed with RC1
PBADEN_OFF_3 EQU 0XFD ; PORTB<5:0> pins are configured as digital I/O on Reset
PBADEN_ON_3 EQU 0XFF ; PORTB<5:0> pins are configured as analog input channels on Reset
CCP3MX_PORTC6_3 EQU 0XFB ; P3A/CCP3 input/output is mulitplexed with RC6
CCP3MX_PORTB5_3 EQU 0XFF ; P3A/CCP3 input/output is multiplexed with RB5
HFOFST_OFF_3 EQU 0XF7 ; HFINTOSC output and ready status are delayed by the oscillator stable status
HFOFST_ON_3 EQU 0XFF ; HFINTOSC output and ready status are not delayed by the oscillator stable status
T3CMX_PORTB5_3 EQU 0XEF ; T3CKI is on RB5
T3CMX_PORTC0_3 EQU 0XFF ; T3CKI is on RC0
P2BMX_PORTC0_3 EQU 0XDF ; P2B is on RC0
P2BMX_PORTB5_3 EQU 0XFF ; P2B is on RB5
MCLRE_INTMCLR_3 EQU 0X7F ; RE3 input pin enabled; MCLR disabled
MCLRE_EXTMCLR_3 EQU 0XFF ; MCLR pin enabled, RE3 input pin disabled
; CONFIG4L Options
STVREN_OFF_4 EQU 0XFE ; Stack full/underflow will not cause Reset
STVREN_ON_4 EQU 0XFF ; Stack full/underflow will cause Reset
LVP_OFF_4 EQU 0XFB ; Single-Supply ICSP disabled
LVP_ON_4 EQU 0XFF ; Single-Supply ICSP enabled if MCLRE is also 1
XINST_OFF_4 EQU 0XBF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
XINST_ON_4 EQU 0XFF ; Instruction set extension and Indexed Addressing mode enabled
DEBUG_ON_4 EQU 0X7F ; Enabled
DEBUG_OFF_4 EQU 0XFF ; Disabled
; CONFIG5L Options
CP0_ON_5 EQU 0XFE ; Block 0 (000800-001FFFh) code-protected
CP0_OFF_5 EQU 0XFF ; Block 0 (000800-001FFFh) not code-protected
CP1_ON_5 EQU 0XFD ; Block 1 (002000-003FFFh) code-protected
CP1_OFF_5 EQU 0XFF ; Block 1 (002000-003FFFh) not code-protected
CP2_ON_5 EQU 0XFB ; Block 2 (004000-005FFFh) code-protected
CP2_OFF_5 EQU 0XFF ; Block 2 (004000-005FFFh) not code-protected
CP3_ON_5 EQU 0XF7 ; Block 3 (006000-007FFFh) code-protected
CP3_OFF_5 EQU 0XFF ; Block 3 (006000-007FFFh) not code-protected
; CONFIG5H Options
CPB_ON_5 EQU 0XBF ; Boot block (000000-0007FFh) code-protected
CPB_OFF_5 EQU 0XFF ; Boot block (000000-0007FFh) not code-protected
CPD_ON_5 EQU 0X7F ; Data EEPROM code-protected
CPD_OFF_5 EQU 0XFF ; Data EEPROM not code-protected
; CONFIG6L Options
WRT0_ON_6 EQU 0XFE ; Block 0 (000800-001FFFh) write-protected
WRT0_OFF_6 EQU 0XFF ; Block 0 (000800-001FFFh) not write-protected
WRT1_ON_6 EQU 0XFD ; Block 1 (002000-003FFFh) write-protected
WRT1_OFF_6 EQU 0XFF ; Block 1 (002000-003FFFh) not write-protected
WRT2_ON_6 EQU 0XFB ; Block 2 (004000-005FFFh) write-protected
WRT2_OFF_6 EQU 0XFF ; Block 2 (004000-005FFFh) not write-protected
WRT3_ON_6 EQU 0XF7 ; Block 3 (006000-007FFFh) write-protected
WRT3_OFF_6 EQU 0XFF ; Block 3 (006000-007FFFh) not write-protected
; CONFIG6H Options
WRTC_ON_6 EQU 0XDF ; Configuration registers (300000-3000FFh) write-protected
WRTC_OFF_6 EQU 0XFF ; Configuration registers (300000-3000FFh) not write-protected
WRTB_ON_6 EQU 0XBF ; Boot Block (000000-0007FFh) write-protected
WRTB_OFF_6 EQU 0XFF ; Boot Block (000000-0007FFh) not write-protected
WRTD_ON_6 EQU 0X7F ; Data EEPROM write-protected
WRTD_OFF_6 EQU 0XFF ; Data EEPROM not write-protected
; CONFIG7L Options
EBTR0_ON_7 EQU 0XFE ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR0_OFF_7 EQU 0XFF ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
EBTR1_ON_7 EQU 0XFD ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR1_OFF_7 EQU 0XFF ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
EBTR2_ON_7 EQU 0XFB ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR2_OFF_7 EQU 0XFF ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
EBTR3_ON_7 EQU 0XF7 ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR3_OFF_7 EQU 0XFF ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
; CONFIG7H Options
EBTRB_ON_7 EQU 0XBF ; Boot Block (000000-0007FFh) protected from table reads executed in other blocks
EBTRB_OFF_7 EQU 0XFF ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
DEVID1 EQU 0X3FFFFE
DEVID2 EQU 0X3FFFFF
[CONFIGEND]

Default Configuration Definitions
[DEFCONFIGSTART]
ifndef CONFIG_REQ
ifdef DEBUG@REQ
CONFIG DEBUG=ON     ; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
else
CONFIG DEBUG=OFF    ; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
endif
ifdef WATCHDOG_REQ
CONFIG WDTEN=ON ; WDT enabled
else
CONFIG WDTEN=OFF ; WDT disabled (control is placed on SWDTEN bit)
endif
ifdef PLL@REQ
CONFIG PLLCFG=ON          ; Oscillator multiplied by 4
else
CONFIG PLLCFG=OFF          ; Oscillator used directly
endif
CONFIG FOSC=HSMP          ; HS oscillator (high power > 16 MHz)
CONFIG XINST=OFF          ; Disabled
CONFIG FCMEN=ON          ; Fail-Safe Clock Monitor enabled
CONFIG IESO=OFF          ; Oscillator Switchover mode disabled
CONFIG PWRTEN=ON          ; PWRT enabled
CONFIG BOREN=ON          ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
CONFIG BORV=190          ; VBOR set to 1.9 V nominal
CONFIG WDTPS=128          ; 1:128
CONFIG MCLRE=EXTMCLR      ; MCLR pin enabled, RE3 input pin disabled
CONFIG HFOFST=OFF          ; The system clock is held off until the HF-INTOSC is stable.
CONFIG PRICLKEN=ON      ; Primary clock enabled
CONFIG PBADEN=OFF          ; PORTB<4:0> pins are configured as digital I/O on Reset
CONFIG CCP2MX=PORTC1      ; CCP2 input/output is multiplexed with RC1
CONFIG CCP3MX=PORTB5      ; P3A/CCP3 input/output is multiplexed with RB5
CONFIG T3CMX=PORTC0      ; T3CKI is on RC0
CONFIG P2BMX=PORTB5      ; P2B is on RB5
CONFIG STVREN=ON          ; Stack full/underflow will cause Reset
CONFIG LVP=OFF          ; Single-Supply ICSP disabled
CONFIG CP0=OFF          ; Block 0 (000800-001FFFh) not code-protected
CONFIG CP1=OFF          ; Block 1 (002000-003FFFh) not code-protected
CONFIG CPB=OFF          ; Boot block (000000-0007FFh) not code-protected
CONFIG CPD=OFF          ; Data EEPROM not code-protected
CONFIG WRT0=OFF          ; Block 0 (000800-001FFFh) not write-protected
CONFIG WRT1=OFF          ; Block 1 (002000-003FFFh) not write-protected
CONFIG WRTB=OFF          ; Boot block (000000-0007FFh) not write-protected
CONFIG WRTC=OFF          ; Configuration registers (300000-3000FFh) not write-protected
CONFIG WRTD=OFF          ; Data EEPROM not write-protected
CONFIG EBTR0=OFF          ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
CONFIG EBTR1=OFF          ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
CONFIG EBTRB=OFF          ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
endif
[DEFCONFIGEND]


[tumbleweed]

I am overheating and so is my PIC!

Is your K22 actually getting hot, or is it just that the freeze spray changes the intosc freq?

If it's getting hot there's something else going on. I've run plenty of the K22 with intosc + PLL @ 64MHz and you'd never even feel a degree of temp rise.

[shantanu@india]

PIC's get hot with reverse supply and short circuited output pin... nothing else can raise their temperature. Check your circuit.

[See_Mos]

Thanks Les, once again!  I will give that a try later.  I do use Config_Start - Config_End normally but tried the old way when I could not get the oscillator to run.

The device is not actually getting hot. Normally my room is about 20 degrees C but yesterday afternoon hit 38 degrees, this morning it's 34 outside already at 11:30 and it is predicted to go over 40 later today, something we are not used to here in the U.K. and I cannot afford the luxury of air conditioning for the few days that it is needed.

The timings that I need are low microseconds or less so I am using DelayCS and trimming the values to take care of the overhead of For-Next loops and other commands, nothing complex just setting and clearing port pins, it is just the temperature drift of the PIC that is causing problems.

[John Lawton]

Is your K22 actually getting hot, or is it just that the freeze spray changes the intosc freq?

If it's getting hot there's something else going on. I've run plenty of the K22 with intosc + PLL @ 64MHz and you'd never even feel a degree of temp rise.

In my experience, there can be significant current consumption on a very busy PIC of that type and slight package warming can occur. In my case the PICs had 16 software PWM lines and fast SPI bus comms so a lot was going on.

[top204]

I know what you mean See_Mos, I cannot afford the luxury of air-con either, so I am sitting here exhausted with the heat.

The internal oscillators on the recent devices (past 10 years or so) are very stable because of their PLL. I have created a few projects that use them and I tested the device with a freezer spray and a hot air gun while transmitting at a very High Baud rate to a serial terminal, and it never faultered and never missed a character. :-) When using the internal oscillator, it is better to up it to 64MHz operation, so a slight drift will not make a lot of difference because the device is operating quite fast for small timings anyway, and the PLL will keep the 64MHz as stable as possible.

Even the microcontrollers and microprocessors that run at many hundreds/thousands of MHz use a PLL mechanism, so a drift in the lower frequency oscillator circuit is compensated for by it.